Many digital circuits receive a clock signal to operate. One type of circuit that receives a clock signal to operate is a memory circuit, such as a dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), or double data rate synchronous dynamic random access memory (DDR-SDRAM). In a memory circuit operating at high frequencies, it is important to have a clock signal that has about a 50% duty cycle. This provides the memory circuit with approximately an equal amount of time on the high level phase and on the low level phase for transferring data into and out of the memory circuit, such as latching rising edge data and latching falling edge data out of the memory circuit.
Often, a clock signal is provided by an oscillator, such as a crystal oscillator, and clock circuitry. The oscillator and clock circuitry may provide a clock signal that does not have a 50% duty cycle. For example, the clock signal may have a 45% duty cycle, where the high level phase is 45% of one clock cycle and the low level phase is the remaining 55% of the clock cycle. A duty cycle corrector receives the clock signal and corrects or changes the duty cycle of the clock signal to provide clock signals with transitions separated by substantially one half of a clock cycle.
One type of conventional duty cycle corrector generates an inverted reference clock from a reference clock using a pair of CMOS delay elements which are adjusted such that each is maintained substantially at one-half a clock cycle of the reference clock so that the inverted reference clock is maintained at 180 degrees out-of-phase with the reference clock. Two delay elements are required since rising and falling edge propagation delays of the reference clock through the delay elements are not equal. The reference and inverted reference clocks are used to generate an output clock have a 50% duty cycle.
While such conventional configurations are effective at providing duty cycle correction, the need for two delay elements consumes a large amount of integrated circuit space. Additionally, due to low chip operating voltages, noise on the chips, and the high operating frequencies of new standards, CMOS delay elements are not always an option as a delay element.